As demands for a smaller electronic device increase, so do the demands for electronic device packaging methods to meet size demands and production efficiency. One method of making a reduced size electronic device is a package-on-package (PoP) method.
The PoP method is an integrated circuit (IC) packaging method that combines vertically discrete components or elements, for example, logic and memory ball grid array (BGA) packages. Two or more packages may be installed on top of each other, i.e. stacked, with an interface to route signals between them. This may allow higher component density in an electronic device, such as, for example, a mobile phone, a personal digital assistant (PDA), and a digital camera.
While the PoP process may be particularly beneficial for space savings in an electronic device, the PoP process may be particularly beneficial as components may be decoupled. In particular, a memory device, for example, may be decoupled from a logic device. Thus, the memory package may be tested separately from the logic package, and only those packages that passed quality checks may be used in final assembly (if the memory is bad, only the memory is discarded and so on). This is in contrast to stacked-die packages, for example, where the entire set of components is useless and rejected if either the memory or logic is bad.
Additionally, a manufacturer of a mobile phone or a digital camera, for example, may control logistics. In other words, one component, for example, the memory, from different suppliers or manufacturers can be used at different times without changing the logic.
Additionally, any mechanically mating top package can typically be used. For example, for a low-end mobile phone, a smaller memory configuration may be used on the top package, while for a high-end mobile phone, more memory could be used with the same bottom package. This may simplify inventory control by the original equipment manufacturers (OEM). In contrast, for a stacked-die package or even package in package (PiP), the exact memory configuration must be known weeks or months in advance.
Electrically, the PoP method may advantageously reduce a length of electrical interconnections (i.e., track length) between different interoperating parts, such as, for example, a controller and a memory. This may improve electrical performance of devices, since shorter routing of interconnections between circuits may yield faster signal propagation and reduced noise and cross-talk. However, electrical interconnections are typically formed at the package level at the surface mounting stage.
U.S. Pat. No. 7,704,796 to Pagaila et al. discloses a semiconductor device, or more particularly, a semiconductor die, that includes recessed conductive vias. Each recessed conductive via is an exterior recess after the wafer is singulated into the semiconductor die.
Further improvements to electronic device packages, for example, PoP packaging, may be desired. More particularly, it may be desirable to reduce overall thickness, increase electrical efficiency, increase production efficiency, and increase mechanical robustness.